gokeshenzhen / TraceWeave
Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM source, hierarchy, and connectivity to trace failures to root cause.
Why this job: says: mcp server; topics: mcp-server, model-context-protocol, mcp
What it does
TraceWeave is an MCP server for RTL / SoC debugging. It connects compile records, simulation logs, VCD/FSDB waveforms, and RTL source to your AI assistant, helping you work from a failed simulation to the relevant time, signals, and driving logic.
Get started
No single install command. Read the steps in the README (opens in new tab)
- Maintenance
- Active
- Last commit 27 days ago
- Stars
- 130
- +2 this week
- Licence
- MIT
- Allows business use
- Downloads for
- None listed
- No release files
- Latest version
- v2.0.2
- Released 2 months ago
- Built with
- Python
- 98% of the code
Is it looked after?
- Contributors
- 1
- Last 90 days
- Issues
- None
- No issues filed
- Pull requests
- 0 merged
- 1 waiting
- Releases
- 3
- 3 in the last year
- No contributing guide
- No security policy
- No code of conduct
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More: languages, topics and project record
Languages
- Python 98%
- C++ 1%
- Shell <1%
Topics
- chip-verification
- eda
- fsdb
- hardware-verification
- llm-tools
- mcp
- mcp-server
- model-context-protocol
- pyslang
- root-cause-analysis
- rtl
- rtl-verification
Project record
- JobMCP servers
- StatusListed
- Commits481
- Forks31
- Watching2
- Stars in 28 days+12
- CreatedFeb 27, 2026
- First seen by usNov 7, 2026
- CheckedNov 7, 2026